The present application claims priority to Japanese Application No. 10-258369 filed Sep. 11, 1998 which application is incorporated herein by reference to the extent permitted by law.
1. Field of the Invention
The present invention relates to a process for producing a semiconductor package and a structure thereof, and particularly, it relates to a process for producing a semiconductor package suitable for a CSP and a structure thereof.
2. Description of the Related Art
In recent years, microminiaturization of a semiconductor package proceeds with miniaturization of an assembled apparatus, and a chip scale package or chip size package (referred to as CSP herein) using a bump connecting technique is developed.
FIGS. 1A and 1B are diagrams showing an example of a related art process for producing a CSP.
As shown in FIGS. 1A and 1B, a bump 102 is formed on a semiconductor wafer 101, which is then die-bonded on a substrate 103. The processing steps after the die bonding are classified into two processes, one of which is shown in FIG. 1A and the other is shown in FIG. 1B.
In the process shown in FIG. 1A, the assembly is sealed with a resin 104, and the wafer 101, the sealing resin 104 and the substrate 103 are subjected to dicing in one piece to complete a CSP 100. The CSP 100 has a layered structure comprising, from the upper side, a semiconductor chip 105, the sealing resin 104 and the substrate 103. (See, for example,
Japanese Patent Laid-Open No. 232256/1997) In the process shown in FIG. 1B, only the wafer 101 die-bonded to the substrate 103 is subjected to dicing, and then sealed with a resin 104. The substrate sealed with the resin is then subjected to dicing to complete a CSP 100.
The process shown in FIG. 1A has the following problems:
(1) Since the substrate and the wafer in one piece are cut, the cutting must be conducted with a blade having a large thickness for cutting a substrate. Such a blade has a thickness of about 150 xcexcm, which is three times or more than that of a blade for cutting a wafer, and therefore kerf loss becomes as large as three times or more.
(2) Since the cutting is conducted by using a blade for cutting a substrate under conditions for cutting a substrate, the semiconductor chip may chipped off.
(3) A flux cleaner and the sealing resin are difficult to penetrate into the inside, and a void (bubble) is difficult to escape (as shown in FIG. 2). Therefore, there is a possibility that on heating in a later step, the void expands to form a crack.
Specifically, in FIG. 2, the both surfaces of the assembly are surrounded by the wafer 101 and the substrate 103 and therefore, only a casting method is effective for sealing with resin 104, in which the resin 104 flows from an inlet 110 to an outlet 111 at an angle xcex8 against the horizontal plane, followed by heating from the side of substrate 103. In this case, in an area where air is entrapped, or in the case where a gas is generated, a void 106 does not escape but remains, resulting in the formation of a crack.
(4) Conduction failure is easily caused by a great influence of warpage of the substrate (as shown in FIG. 3).
Specifically, in FIG. 3, a non-contact part 107 is formed due to a warpage W, resulting in conduction failure. Also, even when the contact is effected, a stress is generated at the bump 102 due to the warpage, resulting in conduction failure, too.
(5) When positional deviation occurs in a die bonding step, all products obtained from the sheet (the semiconductor wafer and the substrate) become defective articles.
The process shown in FIG. 1B has the following problems in addition to the problems (1) to (5):
(6) Since the wafer is fixed only with the bump upon dicing, a crack may be formed at the bump and the dicing contact part due to damage caused by dicing, and thus conduction failure may occur.
(7) The number of dicing steps is larger by once than the process of FIG. 1A.
An object of the invention is to provide a process for producing a semiconductor package and a structure thereof in that an yield per unit area of the wafer is increased, yield and reliability of the product are improved, and the number of processing steps is reduced.
In order to solve the problems described above, the invention relates to a process for producing a semiconductor package comprising a semiconductor chip, a sealing resin and a substrate, which comprises the steps of:
a step of forming a bump on a semiconductor wafer for respective semiconductor chip constituting the semiconductor package;
a step of dicing a substrate, which has been prepared, into a substrate piece corresponding to the respective semiconductor chip;
a step of die-boding the substrate piece, which has been diced, on the semiconductor wafer with making the bump to correspond to the respective semiconductor chip;
a step of sealing a gap between the semiconductor wafer and the substrate piece, which have been die-bonded, with a resin; and
a step of dicing the semiconductor wafer and the substrate piece, which have been sealed with the resin, into the respective semiconductor package.
The invention also relates to a semiconductor package comprising a semiconductor chip constituting the semiconductor package, having equipped therewith a substrate through a bump, the substrate having a size smaller than the semiconductor chip.
According to the process of the invention, only the substrate is cut with a blade having a large thickness for cutting a substrate, and then the semiconductor wafer can be cut with a blade having a small thickness for cutting a wafer. Therefore, the yield of the semiconductor package (semiconductor chip) per unit area of the wafer is increased, and at the same time, chipping off of the semiconductor chip is prevented to increase the yield. Furthermore, since a void escapes from the gap among the substrate pieces on sealing with the resin to eliminate a remaining void, formation of a crack due to the remaining void can be suppressed to improve the reliability.